EDA

ETI’s dual-mode EDA co-verification system is a patented multi/many-core hardware, software and system-level engine used to verify the logic of computer chip designs prior to silicon.

The system co-debugs and co-validates many-core chips using real parallel benchmark programs and real parallel applications, and handles designs of dozens of chips with up to 1000 cores per chip. Winner of the Supercomputing Conference’s Disruptive Technology award, it uses FPGA-based cluster computing for many-core chip/system validation.

Benefits of ETI’s co-verification engine:

• Iterative emulation technology (DIMES mode) provides a foundation for scalable, logic-level emulation of large-scale, many-core components.

• Accelerated Logic Compilation/Synthesis and Simulation (ACCESS mode) technology enables rapid adaptation and verification, and flexible support for architecture and logic modification.

• Co-debugging facilities provide an integrated path for tracing bugs from source code to wire signals.

Contact ETI to see how our specialized expertise and experience can help you take advantage of multi- and many-core environments. We offer a wide range of customizable service arrangements including consulting, training, benchmarking and custom engineering at the hardware and software levels.

White Paper NEW!

SWARM: Scalable Performance Optimization for Multi-core/Multi-node

Datasheet NEW!

SWARM for Application Customers: Scalable Performance Optimization for Multi-core/Multi-node

SWARM beta

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